Single phase seven level Z-source cascaded H-bridge inverter for photovoltaic systems

The Multilevel inverter (MLI) is identified as a viable power electronic unit for distributed energy conversion applications. In this paper discusses the performance of single phase seven level Z (impedance) source cascaded H-bridge inverter topology suited for solar photovoltaic systems. A modified sinusoidal pulse width modulation technique is used to control the switches of the H-bridge inverter. The simulation results are obtained interms of inverter output voltage and harmonic analysis confirm improvement in voltage boost and reduction in harmonic distortion of the suggested inverter topology. The experimental results matches with the simulation values, as verified through a scaled down prototype.


INTRODUCTION
Distributed energy systems employing fuel cell and PV array can easily configure with different topologies of power conversion units for example multilevel inverters are implemented for electrification over the years. Recent advancements of multilevel inverters either in their operating principle and modulation strategy focused for industrial applications and utility systems are found to be interesting and growing for the applicatons of reactive power compensation, renewable energy system power conversion, resonance circuit, UPS power conversion unit and electric-drive vehicles [1][2][3][4][5][6].
Multi-level inverters are designed with photovoltaic voltage source, semiconductor switching device and capacitor, and their performance and output are evaluated by their step. The semiconductor switching device must be able to withstand the voltage surge that occurs when switching switches. The main function of multilevel inverters is to convert the dc power to the desired amount of ac power [7,8]. The topic under study is cascaded multilevel inverter, which is modular in nature and it can be configured with multiple modules [9][10][11][12][13]. Non-transformer power converters are used for the purpose of making such a system low cost, which is the unique function of multilevel inverters are as described in [14][15][16][17][18][19][20]. Merits and demerits of cascaded multi-level inverters are discussed through many applications in [21][22][23][24]. Infusion of Z-source network into the existing multilevel and other inverter topologies improves the voltage boosting capability which can be preferably used for photovoltaic systems [25,26]. In this paper, Z-source Cascaded H-bridge multi-level inverter with symmetric configuration its steady-state operation is discussed in section 2, the  Figure 1 shows the three H-bridges are connected in cascade mode to convert the photovoltaic array dc output to the desired ac power. The output of these three bridges is added together and calculated as the total added value of the inverter. The seven level stepped expression of this system is built in Figure 2.

TOPOLOGY DESCRIPTION: Z-SOURCE CASCADED MLI FOR PV SYSTEMS
Each photovoltaic panel is connected in series and parallel connection mode and their output is connected to each individual H-bridges. The voltage output of H-bridges depends on the value of the photovoltaic system input to them. Also the number of H-bridges depends on the number of photovoltaics array in that system. Better voltage and current can be obtained in sinusoidal design by increasing the levels of the inverter. Also multi-level is considered to be very effective when compared to two level converter. This allows the use of smaller low-pass filters for harmonic reduction [27,28].  Where, N-number of single phase inverter. In other words, a typical cascade MLI requires a photovoltaic arrays for 2 + 1 . If the inverter phase voltage steps is calculated as a value of q, then the line voltage of the inverter is calculated as and also the steps level for three phase different types of load connection can be calculted as The ac output voltage of the each single phase H-bridge inverter and the total sum of output voltage (Vo) value of the multilevel inverter as determined by using (4).
The cascaded H-bridge multi-level inverter desired sinusoidal output voltage can calculate by using using (5).
To design cascaded multilevel inverter required number of switches for each phase or each H-bridge can estimate as per (6).
The operating principle of ZSI Module can be explained as follows. The Z-source inverter is operating at two state of operation such as shoot-through and non-shoot-through states. When the inverter is operating at shoot-through state, the photovoitaic dc output power is coverting into ac power and non-shootthrough states condition the power conversion is zero because of dc-link voltage is zero.
The power balance equation of the each Z-source inverter as Where, νPN and iPN are each H-bridge inverter input voltage and current values, Va and ia are the each H-bridge inverter output voltage and current values and D is a duty ratio of the Z-source inverter.
The Z-source inverter output voltage is determined as XN a P = ν ν m (8) Where m defined as M sin ωt, M -modulation index.
From (7) and (8), PN i is deduced as Both PN I and ̃affect the module variables 1, 2, 1 The impedance design of ZSI network [29] is given by

MODULATION TECHNIQUE
Phase shifted sinusoidal PWM switching strategy can be widely adopted for cascaded ZSI which is based on classical sinusoidal pulse width modulation. Here the triangular signal is taken as the carrier and the signal is compared to the sinusoidal modulating signal. The frequency value of the output voltage of the inverter depends on these two signals. The output frequency value of the inverter can be changed to the desired level by changing the signal frequency of the triangular carrier. The triangular carrier signal frequency is taken as an odd multiplier for the elimination of even harmonics at the output of the inverter.
The triangular carrier signal is (Nc) responsible for the switching losses of the each inverter. So by selecting the right triangular carrier it is possible to get effective inverter output voltage with low conversion losses.
The number of carriers, nc essential to generate m-level inverter output is given by All the triangular carrier signals have the same peak-peak amplitude and frequency which are designated as Ac and fc respectively, whereas the single sinusoidal reference or modulating signal has peakpeak amplitude of Am and carrier frequency fm. Sinusoidal signal as considered as a reference signal is always matched with the carrier sigan of triangular signal. When the sinusoidal signal amplitude is more than the triangular signal amplitude, the swithching pulse is produced and it's given to the inverter gate signal.
The important factors of the modulation procedure [30][31][32][33][34][35][36] are the ratio of the carrier and reference frequency k=fc/fm, where, fc and fm are frequency of the triangular and the sinusoidal signal, respectively. The modulation index M = Am / (m' *Ac), m'= (m-1)/2. Where Am, Ac and m are the modulating signal amplituted, peak-peak triangular signal amplitude and inverter output level, respectively. Traditionally, the output voltage of the inverter can be express in Fourier series expansion as  Table 1 shows the simulation parameters used for the proposed inverter, having DC voltage sources, Z network parameters and a resistive load. Simulations have been developed in MATLAB/SIMULINK environment.

SIMULATIONS AND DISCUSSIONS
The output voltage of the each H-bridge inverter is obtained by employing the gate pulse. The output voltage of the each H-bridge inverter delivers in the shape of alternating quasi-square waveform. Figure 3 shows the switching timings of the inverter to produce a quasi-square output waveform by phase shifted pulse width modulation method for A=5 and f=50.
Various simulated waveforms like boosted DC link voltages, voltage across the three H-bridges, and output AC voltages (Voltage waveform across the three bridges and the load) are shown in Figure 4 and Figure 5.The rms voltage obtained for the proposed inverter is 32.73 V with Z network and 28.88 V without Z network. Adding Z network boosts the voltage by 13.33%. The obtained peak voltage is about 45.27 V with a THD value of 21.20%. Also, the peak voltage across the the three H-bridges are 14 V, 15.27 V and 16.01 V with THD values of 32.21%, 31.17% and 41.44% respectively. However, adding suitable value of inductorfilter will subsequently reduce the THD within 5% with the same peak voltage.

EXPERIMENTAL RESULTS
The proposed seven-level cascaded Z-source inverter circuit has been tested with three DC sources of 12 V with an R load of 50 Ω and the other test parameters used for simulation. The control scheme is programmed with a fixed-point TI-TMS3202812 digital signal processor (DSP) and a programmable logic device. The control signals are sent to insulated gate bipolar transistors (IGBTs) through optical fiber cables. The phase-shifted pulse width modulation technique has been implemented for controlling a seven-level cascaded Z source inverter feeding a resistive load. The sectionalized view of various components present in the overall experimental setup is shown in Figure 8. It consists of a power supply section, provided to give dc supply to the driver circuit and inverter section for energizing the various passive elements present in it. The regulated dc supply of +5 V and ± 15 V is given to the driver circuit IR 2110 and inverter section respectively through IC's LM 7805, LM 7815 and LM 7915 after buffering actions with low noise immunity with respect to output impedance variations. The switching signals to these IGBT switches are given through IR 2110 drivers with autonomous high and low side referenced output channels which operate up to 500 volts with a feature of high pulse current buffer stage designed for minimum driver cross conduction of standard CMOS output, down to 3.3 V logic suitable for inverter applications.
Optoisolator IC TLP 250 is used for gate driving purposes and IC 4506, IC 4081 for buffering actions. Control signals obtained from the FPGA controller are given to the inverter section through these IC's. The inverter circuit module uses IGBT pack namely FSBB20CH60F IC with protection and gate driving functions.XILINX Spartan 3E FPGA XC3S100E, Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due to its fast prototyping, simple hardware, and software design. DC voltage of 12V is given to the three H-bridges individually and the output voltage waveform is observed through a power analyzer generating output magnitude of 38 V with grid frequency nearly 50 Hz which is shown in Figure 9. FFT spectrum of the output voltage waveform is measured showing a THD value of 9.4% as shown in Figure 10. This multilevel inverter has low electromagnetic interference, high operating efficiency, low switching loss, high quality voltage and higher operating voltage. The simulation and hardware results reach a decision to a excessive level. The proposed inverter exhibits well performance and is most suitable for solar photvoltaic applications.