A Novel Multilevel Inverter with Reduced Switch Count

C.R. Balamurugan, K. Vijayalakshmi

Abstract


This paper presents a multilevel inverter with reduced number of switches to produce a five level output. PWM technique (pulse width modulation) has been used to trigger the MLI switches. It gives reduced harmonic. This proposed topology is connected with R-load and RL-load. Four signals are generated for switching on the multilevel inverter (MLI) switches by comparing four level triangular waveform with sine wave. In this proposed topology two switches are reduced from the conventional Cascaded five level inverter. The simulation analysis has been done by MATLAB/SIMULINK.


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